Robust Color Image Encryption Scheme Based on RSA via DCT by Using an Advanced Logic Design Approach

تتزايد أهمية أمن المعلومات في تخزين البيانات ونقلها. من جانب اخر يتم استخدام الصور في العديد من الإجراءات. لذلك ، يعد منع الوصول غير المصرح به إلى بيانات الصورة أمرًا بالغ الأهمية من خلال تشفير الصور لاجل حماية البيانات الحساسة او الخصوصية. تتنوع طرق وخوارزميات إخفاء الصور أو تشفيرها من طرق المجال المكاني البسيطة إلى طرق مجال التردد والذي يعتبر الأكثر تعقيدًا وموثوقية. في هذا البحث ، نقترح نظام تشفير جديد يعتمد على منهجية تهجين مولد المفتاح العشوائي من خلال الاستفادة من خصائص DCT لتوليد مجموعة غير محددة من المفاتيح العشوائية والاستفادة من معاملات المنطقة منخفضة التردد بعد مرحلة DCT لتمريرها إلى نظام فرعي يتكون من مجموعة RLG للحصول على المفاتيح السرية التي يتم تمريرها إلى RSA لتنتهي بتشفير الصورة. تشير النتائج إلى أن الطريقة المقترحة لها القدرة على تولد مجموعة كبيرة جدًا من المفاتيح السرية شديدة التعقيد والآمنة التي يمكن استخدامها لاحقًا في مرحلة التشفير. علاوة على ذلك ، سيتغير عدد وتعقيد تلك المفاتيح في كل مرة يتم فيها تغيير الصورة، وهذا يمثل مساهمة الطريقة المقترحة. ولم نلاحظ اي ضياع للوقت أثناء عمليات التشفير وفك التشفير لاستخدامنا RLG ، مما يدل على أن النظام المقترح قام بعمل جيد في صنع مفاتيح مختلفة من نفس الصورة. ويختلف في قوة المفتاح من صورة إلى أخرى حسب طبيعة الصورة الملونة.Information security in data storage and transmission is increasingly important. On the other hand, images are used in many procedures. Therefore, preventing unauthorized access to image data is crucial by encrypting images to protect sensitive data or privacy. The methods and algorithms for masking or encoding images vary from simple spatial-domain methods to frequency-domain methods, which are the most complex and reliable. In this paper, a new cryptographic system based on the random key generator hybridization methodology by taking advantage of the properties of Discrete Cosine Transform (DCT) to generate an indefinite set of random keys and taking advantage of the low-frequency region coefficients after the DCT stage to pass them to a subsystem consisting of an Reversible Logic Gate (RLG) group to obtain the secret keys that are passed to Rivest Shamir Adleman (RSA) to finish encrypting the image. The results indicate that the proposed method has the ability to generate a very large set of highly complex and secure secret keys that can be used later in the encryption stage. Moreover, the number and complexity of those keys will change each time the image is changed, and this represents the contribution of the proposed method. They experienced no time loss throughout the encryption and decryption processes when using RLG, which indicates that the proposed system did a good job in making different keys from the same image. And it differs in the strength of the key from one image to another, depending on the nature of the color imge

Estimation for Motion in Tracking and Detection Objects with Kalman Filter

The Kalman filter has long been regarded as the optimal solution to many applications in computer vision for example the tracking objects, prediction and correction tasks. Its use in the analysis of visual motion has been documented frequently, we can use in computer vision and open cv in different applications in reality for example robotics, military image and video, medical applications, security in public and privacy society, etc. In this paper, we investigate the implementation of a Matlab code for a Kalman Filter using three algorithm for tracking and detection objects in video sequences (block-matching (Motion Estimation) and Camshift Meanshift (localization, detection and tracking object)). The Kalman filter is presented in three steps: prediction, estimation (correction) and update. The first step is a prediction for the parameters of the tracking and detection objects. The second step is a correction and estimation of the prediction parameters. The important application in Kalman filter is the localization and tracking mono-objects and multi-objects are given in results. This works presents the extension of an integrated modeling and simulation tool for the tracking and detection objects in computer vision described at different models of algorithms in implementation systems

Optimisation d'une bibliothèque de modules matériels de traitement d'images (conception et test VHDL, implementation sous forme FPGA)

Le traitement d'images en temps réel conduit à utiliser des circuits électroniques rapides, capables de manipuler les grandes quantités d'informations générées par une source vidéo. Pour cela, les circuits logiques programmables sont particulièrement adaptés. Une première application consiste à la réalisation d'une carte d'acquisition, traitement et restitution du signal vidéo. Cette carte contient un FPGA Xilinx XC4010E permettant l'implémentation d'algorithmes pour le test et traitement d'images. Une deuxième application, utilisant la carte de développement Excalibur d'Altera à base du FPGA Apex20KE et contenant le processeur embarqué NIOS, consiste à la conception d'un SOPC avec des fonctionnalités matérielles et logicielles tout en utilisant des IPs pour les périphériques de la carte et la description des interfaces Caméra et VGA pour l'acquisition et la restitution du signal vidéoReal time image processing requires the use of quick electronic circuits, which are able to handle the big quantities of information generated by a video source. As a consequence, the FPGA are particularly adapted. A first application consists of the realization of a card for acquisition, treatment and restitution of the video signal. This card contains an FPGA Xilinx XC4010E allowing the implementation of algorithms for the test and image processing. A second application, using the Altera-Excalibur development kit based on FPGA Apex20KE which contain the NIOS embedded processor, consists of the SOPC conception with hardware and software functionalities, all while using IPs for the peripherals of the card and the description of the Camera and VGA interfaces for acquisition and restitution of the video signal.BORDEAUX1-BU Sciences-Talence (335222101) / SudocSudocFranceF

Approximation Algorithm for Scheduling a Chain of Tasks for Motion Estimation on Heterogeneous Systems MPSoC

Co-design embedded system are very important step in digital vehicle and airplane. The multicore and multiprocessor SoC (MPSoC) started a new computing era. It is becoming increasingly used because it can provide designers much more opportunities to meet specific performances. Designing embedded systems includes two main phases: (i) HW/SW Partitioning performed from high-level (eclipse C/C++ or python (machine learning and deep learning)) functional and architecture models (with virtual prototype and real prototype). And (ii) Software Design performed with significantly more detailed models with scheduling and partitioning tasks algorithm DAG Directed Acyclic Graph and GGEN Generation Graph Estimation Nodes (there are automatic DAG algorithm). Partitioning decisions are made according to performance assumptions that should be validated on the more refined software models for ME block and GGEN algorithm. In this paper, we focus to optimize a execution time and amelioration for quality of video with a scheduling and partitioning tasks in video codec. We show how they can be modeled the video sequence test with the size of video in height and width (three models of scheduling tasks in four processor). This modeling with DAG and GGEN are partitioning at different platform in OVP (partitioning, SW design). We can know the optimization of consumption energy and execution time in SoC and MPSoC platform

Etude Comparative de deux Processeurs Softcores NIOS II et LEON 3

International audienceCet article présente une étude comparative entre deux processeurs softcores NIOS II d’ALTERA et LEON 3 de Gaisler Research. Notre comparaison porte sur deux critères qui sont le nombre de ressources occupées par chacun des deux processeurs softcores et cela à travers les résultats de synthèse réalisée avec Quartus II et la performance à travers les résultats obtenus avec la suite de benchmark STANFORD. Cette comparaison nous a permis de constater que LEON 3 offre des performances en terme de puissance de calcul plus importantes que celles obtenues avec NIOS II, mais cela contre une occupation des ressources supérieure à celle obtenues avec NIOS II

An FPGA implementation of HW/SW codesign architecture for H.263 video coding

International audienceIn this paper, we present an efficient HW/SW codesign architecture for H.263 video encoder and its FPGA implementation. Each module of the encoder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portions include the Discrete Cosine Transform (DCT), inverse DCT (IDCT), quantization (Q) and inverse quantization (IQ). Remaining parts were realized in software executed by the NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT/IDCT is suggested to reduce the chip size. A NIOS II Custom instruction logic is used to implement Q/IQ. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design is described in VHDL language, verified in simulations and implemented in Stratix II EP2S60 FPGA. Finally, the encoder has been tested on the Altera NIOS II development board and can work up to 120 MHz. Implementation results show that when HW/SW codesign is used, a 15.8-16.5 times improvement in coding speed is obtained compared to the software based solution

REAL-TIME VIDEO SYSTEM DESIGN BASED ON THE NIOS II PROCESSOR AND μCLINUX

International audienceIn this paper, a modular, configurable and versatile hardware platform for real-time video and image processing is presented. The hardware platform is based on the Altera STRATIX development board which is completed with a Camera interface for video acquisition and a VGA interface for image restitution. The platform supports simultaneous HW/SW co-design and partitioning. The system main part is the Altera NIOS II soft core processor for data processing. During this study, we have used video sequences, which are acquired, processed and visualized while respecting temporal constraints. The whole of system was made under μClinux and was performed on the NIOSII soft core processor. Simulation and Synthesis results are presented and prove tha

HW/SW Codesign of the H. 263 Video Coder

International audienceIn this paper, we propose an optimized real-time H.263 video coder. The coder has been implemented in one FPGA device as HW/SW partitioned system. We made time analysis and optimization of the H.263 coder. On the basis of the achieved results, we decided for hardware implementation of the discrete cosine transform (DCT).Remaining parts were realized in software with NIOS II softcore processor. H.263 coder (NIOS II processor, DCT core) has described by the VHDL language and implemented in Stratix EP1S10 FPGA. Finally, the coder has been tested on the Altera Stratix development board